Design of CMOS Current Comparator for High Speed and Low Power Applications

Pages:78-81
Priyanka Kaswan and Supriya (Department of Electronics & Communication Engineering, Prannath Parnami Institute of Management & Technology, Hisar, Haryana)

This paper presents a CMOS current comparator with high speed and low power consumption having minimum circuit complexity. Circuit shows a low response time to provide high speed. SPICE is used to verify the circuit performance with a standard 0.5μm and 0.35 μm CMOS technology. Circuit with 0.5μm CMOS technology shows the propagation delay of 292.19 ps to 10.10 ns and total power dissipation of 12.19 mW to 854.69 nW for input current pulse of 1 mA to 1 μA. Similarly circuit with 0.35 μm CMOS technology shows the propagation delay of 390.15 ps to 20.223 ns and total power dissipation of 7.37 mW to 572.88 nW for input current pulse of 1 mA to 1 μA. Comparisons have been made with the earlier circuit for power dissipation and delay. It has been observed that present circuit shows better performance than previous circuit.