Reduction of Power Dissipation in CMOS Devices using Dual-Threshold Voltage Techniques

Pages:18-27
Suman Gill, Munna Devi and Rajesh Kumar (Department of Electronics & Communication Engineering, Manav Institute of Technology & Management, Jevra, Hisar, Haryana)

The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. Dual threshold voltage (DVT) domino logic utilizes dual Vt’s to provide the performance equivalent of a purely low Vtdesign with the standby leakage characteristic of a purely high Vtimplementation. DVT domino logic is an attractive circuit style compared to other dual Vttechniques because there are no performance penalties, no difficult transistor sizing issues, and all gates (not just non-critical ones) can be compensated.