Design and Analysis of Half Subtractor Using GDI Technique

Pages:20-23
Parmeela Pachar, Suman Rani and Jai Parkash Godara (Department of Electronics and Communication, PPIMT Hisar, Haryana)

Since there are many advancement in the VLSI technology and there are many efficient styles of designing VLSI circuits like CMOS, PTL, CPL, TG etc. In this paper GDI technique is described. This technique helps in designing low power digital combinatorial circuits by which we can eradicate the demerits of CMOS, TG techniques. Half subtractor using this technique is designed and presented in this paper. This consumes less power in comparison to CMOS and TG techniques. The proposed half subtractor circuit consists of 6 transistors. The circuit is designed and simulated using DSCH 3.5 and MICROWIND 3.5 on 45 nm. The proposed circuit has been compared with respect to the transistor count, area and power dissipation with the CMOS and TG technique.